1. Field of Art
The disclosure generally relates to the field of simulation and verification of a circuit design and more specifically to adapting a testbench of a downstream module to be compatible with a current module under test.
2. Description of the Related Art
In the design of custom integrated circuits, a design is oftentimes hierarchically subdivided into various blocks. The outputs of one block may be used as the input for another block. Furthermore, a target performance is then specified for each of the blocks of the design of the custom integrated circuit. In the design of a larger integrated circuit, the different blocks may be assigned to different design engineers. In this scenario, the design of some blocks may become complete before others. Moreover, different blocks may have different sensitivities to various process, voltage, temperature, and load variations, leading to different verification strategies.
During the design of a downstream block, the designer may make certain assumptions on the variation for the inputs of the block, which correspond to variation in the upstream blocks. The designer of the downstream block may then design the block based on those assumptions. After the upstream blocks are finalized, the designer of the downstream block may verify the performance of the block based on the actual performance of the upstream block. That is, the downstream block may be verified using the simulation results of the upstream blocks.
However, the verification of the downstream block is oftentimes difficult to achieve due to each block being designed by separate engineers, often in separate geographical locations, and verified under different set of corner condition for process and environment as a result of the differing verification strategies. For example, some blocks are verified under a wide range of temperatures and a narrow range of power supply voltages, while other are verified under a narrow range of temperature and a wide range of power supply voltages. Furthermore, measurements and variables names may differ from block to block. As such, this may create data access and data alignment problems that complicate the verification of the custom integrated circuit.